Many electrically programmable read only memory (EPROM) devices are of the virtual or decoded ground design. Virtual ground EPROMs are disclosed in U.S. Pat. No. 3,934,233 issued to Fisher and Rogers, U.S. Pat. No. 4,021,781 issued to E. R. Caudel, and U.S. Pat. No. 4,281,397 issued to Neal and Reed, all assigned to Texas Instruments.
Memory cells in virtual ground arrays are arranged in rows and in columns orthogonal to the rows. Adjacent columns of the memory cells share a bit line, such that first ends of the current paths of an adjacent pair of cells on any one row are connected to one bit line. The other ends of the current paths of the cells are connected to different array sources or decoded ground lines.
In order to read a cell, an array source or decoded ground on one end of a current path of a selected memory cell is brought low. The bit line is connected to a voltage bias source. If the memory cell is conductive, a current flows from the bit line to the array source of the memory cell. The conductance state of the memory cell may be ascertained by sensing the voltage level of the bit line.
If a memory cell is to be programmed, the array source is also brought low, and the bit line is connected to a source of a relatively high voltage, such as approximately 12 volts. Note that in this instance, the current flow direction is also from the bit line to the array source of the memory cell. Arranged in this manner, the memory cells have dedicated drain and source paths, where the current always flows in the same direction.
It is desirable to keep the voltage level on the bit line or the drain as low as possible during read mode to reduce or eliminate a hot electron effect, by which electrons enter the floating gate from the channel of the device, "read disturbing" the state of the memory cell. However, it is also desirable to raise the voltage level on the bit line to lower the junction capacitance of the drain. The drain of a device should be constructed to optimize device programming, but such optimization also exacerbates "read disturb." It seems, from the foregoing, that because of the different and contradicting requirements for reading and programming memory cells, a memory device having optimal reading and programming characteristics is not possible.
The present invention is directed to overcoming the above problems.